Semiconductor memory devices, such as DRAM, SRAM, EPROM, and/or FLASH, include an integrated circuit that stores data and/or code. In certain applications, loss of any of the data and/or code may require a manufacturer and/or end user to replace the memory, which is costly. As such, reliability of the memory is important.
Semiconductor memory typically includes defects that occur during the manufacturing process. Typically, one or more memory locations (i.e., bit addresses) may be defective. Data may not be correctly written and/or read from these locations, which adversely affects the operation of the system that includes the memory.
Referring now to FIG. 1, an exemplary computing device 10 includes a system on chip (SOC) 12 and a memory module 14 that are mounted on a printed circuit board 15 or within a multi-chip-module (MCM) package. For example, the computing device 10 may be a component of a mobile computing device, a cellular phone, a laptop computer, and/or any other computing device, or the computing device 10 may be a device applying MCM package technology that can be used as a component in a system. The SOC 12 includes a processor 18, an input/output (I/O) interface 20, and other SOC components 22 for interfacing with the processor 18 or otherwise communicating with the computing device 10. The processor 18 interfaces with the memory module 14 and the other components 22 of the computing device 10. The computing device 10 may also include other I/O devices 24 that interface with the memory module 14 and the components of the SOC 12.
Referring now to FIG. 2, an alternative arrangement of an SOC 32 and a memory module 34 is shown. The memory module 34 is integrated with the SOC 32 (in other words, the memory module 34 is embedded).
Referring now to FIG. 3, data is stored in the memory module 40 according to memory addresses. The memory addresses define specific storage locations of data bits in memory 40. For example, the memory module 40 includes memory banks 42-1, 42-2, . . . , and 42-x (referred to collectively as memory banks 42). Each memory bank 42 includes address rows 44-1, 44-2, . . . , and 44-y, referred to collectively as address rows 44, and address columns 46-1, 46-2, . . . , and 46-z (referred to collectively as address columns 46). Data bits that are stored in the memory module 40 are stored according to specific address rows 44 and address columns 46 in each memory bank 42.
Various methods are used to correct defects and improve memory yield. Referring now to FIGS. 4A and 4B, a memory module 50 may include redundant memory elements. When certain bit locations are defective, the redundant memory elements are used to replace the defective bit locations. The memory module 50 includes memory banks 52, address rows 54, and address columns 56 as described above in conjunction with FIG. 3. Additionally, each memory bank 52 includes redundant address rows 58-1, 58-2, . . . , and 58-m (referred to collectively as redundant address rows 58), and/or redundant address columns 60-1, 60-2, . . . , and 60-n (referred to collectively as redundant address columns 60).
Initially, the bit locations provided by the redundant address rows 58 and address columns 60 are not associated with a particular memory address. A redundant memory circuit 62 communicates with the memory module 50. The redundant memory circuit 62 programs the redundant address rows 58 and address columns 60 to correspond to a specific memory address when a bit location associated with the memory address is found to be defective. For example, the redundant memory circuit 62 may include fuses 63-1, 63-2, . . . , and 63-a, referred to collectively as fuses 63 (e.g., laser fuses and/or electrical fuses). An external memory repair device 64 is connected to the redundant memory circuit 62 to determine a defective bit location associated with a memory address. The memory repair device 64 blows the one or more of the fuses 63 (i.e., applies a laser or electrical current to the fuses 63) to form a new data path to the redundant location. Thereafter, data that is directed to be stored at the memory address will be stored in the redundant location. In this manner, an originally defective memory device is repaired and is suitable to be used and/or sold.
Referring now to FIG. 4B, an exemplary redundant memory circuit 62 is shown in further detail. Signals 65-1, 65-2, . . . , and 65-b, referred to collectively as signals 65, are indicative of memory addresses of defective memory locations. For example, the signals 65 may be indicative of a defective address row. The redundant memory circuit 62 receives the signals 65 and a repair signal 66 from the memory repair device 64. The signals 65 are input to a redundant row decoder 67. The redundant row decoder 67 communicates with a redundant row 68 according to statuses of the fuses 63. As described above, the memory repair device 64 may be used to blow one or more of the fuses 63 to program the redundant row decoder 67 to associate a particular memory address with the redundant row 68. A similar approach may be used for redundant columns.
The above-described memory repair operation results in a permanent re-association of the memory address with the redundant location. The memory repair operation permanently changes the electrical behavior of the fuse element. In the case of a laser fuse, a high energy laser beam cuts through the fuse (i.e., a conductive fuse element is rendered non-conductive as a result of the memory repair operation). In the case of an electrical fuse, an electric pulse or pulses are applied to the fuse element. As a result, the fuse element changes from conductive to non-conductive or from non-conductive to conductive.
Referring now to FIG. 5, a memory module 70 includes memory banks 72. Each memory bank 72 includes memory blocks 74-1, 74-2, . . . , and 74-p, referred to collectively as memory blocks 74. Each memory block 74 includes address rows and columns as described above. A redundant memory block 76 functions as a redundant memory element. The redundant memory block 76 includes redundant address rows and columns as described above.
Referring now to FIG. 6, a memory module 80 includes memory banks 82-1, 82-2, . . . , and 82-q (referred to collectively as memory banks 82). Additionally, the memory module 80 includes a redundant memory bank 84. The redundant memory bank 84 includes redundant address rows and columns as described above.
Typically, semiconductor memory devices are tested after the manufacturing process and prior to being sold. For example, the semiconductor devices are tested according to a wafer sort and/or final test. The wafer sort and final test procedures determine functionality of all bits of the memory device. Subsequently, defective bits are detected and recorded. The defective bits are compared to the storage capabilities of the redundant memory elements. If there are enough redundant memory elements to compensate for the defective bits, a memory repair operation is performed as described above to re-associate the memory addresses of the defective bit locations with the redundant memory elements.
In certain situations, memory elements are not initially defective and instead materialize as latent defects. Latent defects become known after the memory device is used in the field. To detect potential latent defects during manufacturing, a “burn-in” procedure is applied. For example, a voltage is applied to the memory devices while operating at a high environmental temperature (e.g., 125° C.). Subsequent tests are then able to detect the latent defects. If there unused redundant memory elements remaining, additional memory repair operations may be performed.
The above-described burn-in procedure requires the use of ovens and burn-in boards, which can be costly. When the memory device is embedded in a SOC product, the burn-in boards are not reusable, which further increases expense. The burn-in procedure may require anywhere from 8 to 72 hours to reveal the latent defects. As such, the burn-in procedure increases manufacturing time and cost.
Burn-in does not always detect all latent defects. Therefore, defective memory locations might not be revealed until later in the system manufacturing process, during a packaging process, and until after sale. When a defective memory device is found during the system manufacturing process, the defective memory device may be replaced. The later in the procedure that defective memory elements are detected and replaced, the greater the cost to the manufacturer.